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ARA2001S23
CATV Reverse Amplifier with Step Attenuator Advanced Product Information - Rev. 2
FEATURES * * * * * * * * * * Low cost integrated monolithic GaAs amplifier with step attenuator. Attenuation Range: 0 58 dB, variable in 1 dB steps via 8 bit serial input. Meets DOCSIS distortion requirements at +60 dBmV Low distortion & Low noise figure Frequency range: 5 100 MHz 5 Volt operation APPLICATIONS MCNS/DOCSIS Compliant Cable Modems CATV Interactive Set-Top Box Telephony over Cable Systems Open Cable Set-Top Box
S23 28 PIN SSOP PACKAGE
Description The ARA2001S23 is a GaAs IC designed to provide the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. This part is a balanced design that meets or exceeds the MCNS/DOCSIS requirement for harmonic performance @ +60dBmV output levels while only requiring a single polarity +5V supply. Both the input and output are matched to 75 ohms. The precision attenuator provides up to 58 dB of attenuation in 1 dB increments. The ARA2001S23 is supplied in a 28-pin SSOP package featuring a thermal heat slug on the bottom of the package. Soldering this heat slug to the ground plane of the PC board ensures the lowest possible thermal resistance for the device resulting in a long MTF.
Tx Enable/Disable Gain Control
DAT CLK "Shutdown" EN
CMOS IC Upstream QPSK/ 16-QAM Modulator
PA ~ PA ARA2001 Reverse Amp
Low Pass Filter Balun ATTN 1/2/4/8/16/32 dB
PA
Low Pass Filter
~
PA Clock Data Microcontroller w/Enet MAC RAM ROM
MAC "Shutdown" Clock 45 MHz IF Data
Diplexer Filter
54-860 MHz
Double Conversion Tuner
SAW
QAM Receiver w/FEC
10Base-T Tranceiver
RJ45 Connector
Coax Input
Figure 1: Cable Modem or Interactive Set-Top Box Block Diagram
ARA2001S23
GaAs IC
Attn In Amp Out Amp In Attn Out Amp In Amp Out
32 dB
16 dB
8 dB
4 dB
2 dB
1 dB
ISET 1 Control 1 Amp In Amp Out Attn In
EFET
ISET 2
EFET
Control 2 Amp Out Amp In Attn Out
32 dB P5
16 dB P4
8 dB P3
4 dB P2
2 dB P1
1 dB P0
Buffer
Clock
8
Data
8-Bit Shift Register
Control Latch
Enable
CMOS IC (Serial to Parallel Interface)
Figure 2: ARA 2001 Block Diagram
ABSOLUTE MAXIMUM RATINGS PARAMETER
V DD (P INS 2,4,9,21,24) V RFIN (P INS 5,8) ATTIN (3,10) ATTOUT (19,26)V ISET (P INS 7, 22)
RF Input Voltage (P INS 5,8)*
PARAMETER
9 0 to -3 5 2 + 60 - 55 to +200 260 5 0 to + 85 VD C VD C VD C VD C dB mV C C S ec C
Storage T mperature e S olderi ng T mperature e S olderi ng Ti me Operati ng C ase T mperature e
2
ARA2001S23
ELECTRICAL CHARACTERISTICS (TYPICAL) (VDD=5 VDC, TC=25 C)
PAR AMETER Gai n 1 @ 10 MHz Gai n Flatness
1
MIN 27.5 0.65 1.6 3.6 7.5 15.0 30.2 10 MHz 10 MHz 78 3 -
TYP 29.3 0.75 -0.006 0.83 1.70 3.75 7.75 15.40 30.75 -75 -60 68.5 3.0 65 75 -20 -5 75 -17 -15 5 5 48
MAX 30.5 1.00 2.05 4.0 8.0 15.8 31.3 -53 -53 4.0 -25.5 -40.8 -12 -12 -10 7 5 80
U N IT dB dB dB/c
C OMMEN TS At 0dB attenuati on setti ng 5 to 42 MHz
Gai n Vari ati on Over Temp Attenuati on Steps
1
1 dB 2 dB 4 dB 8 dB 16 dB 32 dB
dB
2nd Harmoni c D i storti on Level 2 3rd Harmoni c D i storti on Level 2 3rd Order Output Intercept Poi nt 1 dB Gai n C ompressi on Poi nt Noi se Fi gure1
dB c dB c dBmV dBmV dB dBmV
at +60 dBmV at +60 dBmV
Includes i nput balun loss Any 3200 KHz bandwi dth from 5-42 MHz D i fference i n output si gnal level between Tx enable / di sable
Ouput Noi se Power Acti ve/No Si gnal/Mi n Attn. Setti ng Acti ve/No Si gnal/Max Attn. Setti ng Isolati on i n Tx di sable mode @ 45 MHz Input Impedance1 Input Return Loss1 Input Return Loss 1 Output Impedance1 Output Return Loss1 Output Return Loss1 VDD1, VDD2 (Pi ns 4, 9, 21, 24) VDD D i gi tal (Pi n 2) VDD C MOS (Pi n 11) I DD1 (Input Amp) (Pi ns 4 and 9)
dB ohm dB dB ohm dB dB V V V mA
Tx enabled Tx di sabled
Tx enabled Tx di sabled
Tx enabled
3
ARA2001S23
ELECTRICAL CHARACTERISTICS (TYPICAL) (VDD=5 VDC, TC=25 C) (Continued)
PAR AMETER I DD1 I DD2 (Output Amp) (Pi ns 21 and 24) I DD2 I DD D i gi tal (Attenuator) (Pi n 2) Power C onsumpti on Power C onsumpti on Attenuator Step Si ze Gai n Flatness
1
MIN 0.6 58.6
TYP 2.4 77 3.7 9 0.67 75 1.5 4 60.3
MAX 6 120 9 15 1.08 150 1.4 100 7
U N IT mA mA mA mA W mW dB dB mVp-p -
C OMMEN TS Tx di sabled Tx enabled Tx di sabled
Tx enabled Tx di sabled
5 - 65 MHz At 0 db Attenuator Setti ng At 24 db Attenuator Setti ng
Output Voltage Transi ent 1 Tx enable/di sable Maxi mum Attenuati on
Notes: 1. As measured in ANADIGICS test fixture 2. At +60 dBmV output level into 75 ohm load
Attenuation Level vs Control Word
64 60 56 52 48 44 Attenuation (dB) 40 36 32 28 24 20 16 12 8 4 0 0 4 8 12 16 20 24 28 32 Control Word 36 40 44 48 52 56
4
ARA2001S23
Gain & Noise Figure vs Frequency
35 8
30
7
25
6
Gain (dB)
20
5
15
4
10
3
5 10 20 30 40 50 60 70 80 90
2 100
Gain
Noise Figure
Frequency (MHz)
Gain & Noise Figure vs VDD
35 6
32
5
GAIN (dB)
29
4
26
3
23 Measured @ 30 MHz 20 3 Gain 4 Noise Figure 5 6 7
2
1
VDD ( Volts )
G AIN & Noise Figure vs Tem perature
35 6
32
5
GAIN (dB)
29
4
26
3
23
2
Measured @ 30 MHz 20 -40 -25 Gain -10 N oise Figure 5 20 35
o
1 50 65 80
Tem perature (C )
NF (dB)
NF (dB)
NF (dB)
5
ARA2001S23
Harmonic Distortion vs VDD
Pout = 58 dBmV
-20
-30
Harmonic Level (dBc)
-40
-50
-60
-70
Measured @ 5 MHz
-80 3 4 5 6 7
2nd Harmonic
3rd Harmonic
VDD ( Volts )
Harmonic Distortion vs VDD
-20
Pout = 58 dBmV
-30
Harmonic Level (dBc)
-40
-50
-60
-70 Measured @ 12 MHz -80 3 2nd Harmonic 4 3rd Harmonic 5 6 7
VDD ( Volts )
Harmonic Distortion vs Temperature Pout = 58 dBmV
-40 -45 -50
Harmonic level (dBc)
-55 -60 -65 -70 -75 Measured @ 5 MHz -80 -40 -25 -10 3rd Harmonic 5 20 35
o
50
65
80
2nd Harmonic
Temperature (C )
6
ARA2001S23
Harmonic Distortion vs Power Out
-30 -35
-40
Harmonics (dBc)
-45
-50
-55
-60
-65
-70
-75 49 2nd 51 3rd 53 55 57 59 61 63 65 67
Pout (dBmV)
Measured @ 10 MHz Transients vs Attenuation
Pout = 55 dBmV at 0dB attenuation.
100 90 80 70
Transient (mV)
60 50 40 30 20 10 0 0 10 20 30 40 50 60
Power Attenuation (dB)
DOCSIS 1.1 Spec. ARA2001
7
ARA2001S23
Harmonic Performance vs Frequency Pout = +62 dBmV
-50 -52 -54
Harmonic Level (dBc)
-56 -58 -60 -62 -64 -66 -68 -70 -72
5
10
15
20
25
30
35
Frequency (MHz) 2nd Harmonic 3rd Harmonic
IIP2 & IIP3 vs Frequency
40 14
36
12
IIP2 (dBm)
28
8
24 Measured @ VDD = 5 Volts Pin = -20 dBm per tone 20 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95
6
4 100
Frequency (MHz)
IIP2 IIP3
IIP2 & IIP3 vs VDD
40 15
36
11
IIP2 (dBm)
28
3
24 Measured @ 65 MHz Two tones @ 29.5 MHz & 35.5 MHz Pin = -20 dBm per tone 20 3 4 5 6 7
-1
-5
VDD (Volts)
IIP2 IIP3
8
IIP3 (dBm)
32
7
IIP3 (dBm)
32
10
ARA2000 & 2001 Balanced Reverse Amp Test Fixture with 3 Wire Interface
+5V (Vdd2)
+5V (Vdd1 & Vattn)
0.1uF
1uF
1uF
0.1uF
10uH 1000pF 1200 ohms 1000pF
1 2 3 4 5 6
gnd Vattn Attn In + Out A1 + In A1 + Vg1 SB1 In A1 Out A1 Attn In Vdd CMOS Clock Data Enable
gnd
28 27 26 25 24 23 22 21 20 19 18 17 16 15
470pF
TEST CIRCUIT
Attn Out + In A2 + Out A2 + Vg2 SB2 Out A2 In A2 Attn Out Gnd CMOS nc nc nc
1:2 RF Input (75 ohm)
2:1
1500pF R
3.9 ohms
7 8
Toko Balun P/N 616PT-1030 470pF
1200 ohms 1000pF 2K ohms 1000pF
9 10 11 12
Toko Balun P/N 616PT-1030 470pF 2K ohms 470pF
10uH
13 14
1K ohm 2K ohms
0.1uF
1uF
0.1uF
1uF
Vdd CMOS
ENABLE
CLOCK
DATA
Control A1 0 / +3 V
+5V (Vdd1)
Control A2 0 / +3 V
2K ohms
1K ohm
Note: Tx Enable = Control Tx Disable = Control 1
ARA2001S23
9
ARA2001S23
Programming Word
D0
P0
D1
P1
D2
P2
D3
P3
D4
P4
D5
P5
D6
P6
D7
P7
Data Port Description
SERIAL DATA P0 P1 P2 P3 P4 P5 P6 P7 FUNCTION 1 dB Attenuator Bit 2 dB Attenuator Bit 4 dB Attenuator Bit 8 dB Attenuator Bit 16 dB Attenuator Bit 32 dB Attenuator Bit N/A N/A
Figure 3
SERIAL DATA INPUT TIMING
DATA
D7: MSB
D6
D5
D4
D1
D0: LSB
CLOCK
ENABLE OR ENABLE
Figure 4
10
ARA2001S23
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function Ground VATTN ATTIN (+) A1
OUT
D escription
Supply for Attenuator Attenuator Input (+) Ampli fi er 1 (+) Output Ampli fi er 1 (+) Input Ampli fi er A1 (+/-) C ontrol Ampli fi er A1 (+/-) C urrent Adjust Ampli fi er A1 (-) Input Ampli fi er A1 (-) Output Attenuator Input (-) Supply For D i gi tal C MOS C i rcui t C lock D ata Enable No C onnecti on No C onnecti on No connecti on Ground for D i gi tal C MOS C i rcui t Attenuator Output (-) Ampli fi er A2 (-) Input Ampli fi er A2 (-) Output Ampli fi er A2 (+/-) C urrent Adjust Ampli fi er A2 (+/-) C ontrol Ampli fi er A2 (+) Output Ampli fi er A2 (+) Input Attenuator Output (+) No C onnecti on Ground
(+)
A 1IN (+) V g1 ISET1 A 1IN (-) A 1OUT (-) ATTIN (-) C MOS C LK D AT En N/C N/C N/C C MOS ATTOUT (-) A 2IN (-) A 2OUT (-) ISET2 V g2 A2
OUT
(+)
A2
IN
(+)
ATTOUT (+) N/C GND
11
ARA2001S23
Package Outline
SYMBOLS
DIMENSIONS IN INCHES
DIMENSIONS IN MILLIMETERS
A A1 A2 b C D E H e L y T S
MIN 0.057 0.000 0.057 0.008 0.007 0.386 0.150 0.228 0.025 0.016 --- 0 --- ---
MAX 0.061 0.004 0.012 0.010 0.394 0.157 0.244 0.050 0.004 8 0.190 0.096
MIN 1.45 0.00 0.20 0.18 9.80 3.81 5.80 0.40 --- 0 --- ---
1.45
MAX 1.55 0.10 0.30 0.25 10.00 4.00 6.20 1.27 0.10 8 4.82 2.43
NOTE 1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH AND GATE BURRS 2. TOLERANCE 0.004in.[0.10 mm] UNLESS OTHERWISE SPECIFIED 3. CONTROLLING DIMENSION ARE INCHES. 4. REF. - MO-137
.64
12
ARA2001S23
NOTES
13
ARA2001S23
NOTES
14
ARA2001S23
NOTES
15
ARA2001S23
ANADIGICS, Inc. 35 Technology Drive Warren, New Jersey 07059 Tel: (908) 668-5000 Fax: (908) 668-5132 http://www.anadigics.com Mktg@anadigics.com
IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or discontinue any product at any time without notice. The Advanced Product data sheets and product specifications contained in this data sheet are subject to change prior to a products formal introduction. The information in this data sheet has been carefully checked and is assumed to be reliable. However, ANADIGICS assumes no responsibility for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.
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